This invention relates in general to comparators and in particular to a high-speed comparator comprising a regenerative latch with offset cancellation.
In the application specific integrated circuit (ASIC) industry, it is desirable to integrate an entire system or subsystem on one integrated circuit chip. The ability to so integrate increases the economy and reliability of the system or subsystem. However, to take advantage of this integration, all the system components are preferably implemented in the same process technology. Such integration becomes a significant problem, for example, in the case of mixed analog and digital systems. One way to integrate mixed analog and digital systems on one chip is to employ a special process technology for the analog systems in addition to the process technology for the digital portion of the chip. For most ASIC chips, only a small portion of the chip is used for analog circuits while by far the greater portion of the chip is used for digital circuits. Hence, devoting a special process technology for adding analog process modules in the digital process, such as capacitor implants and double poly, is expensive. One solution to the problem is to design certain analog components in the digital process. In this approach, careful circuit design is necessary to overcome the large offset voltages, and unpredictable amplification and lack of a good capacitor in a typical digital technology.
The comparator is a frequently used analog circuit on ASIC chips; for example, it is used in analog to digital converters. Therefore, it is desireable to provide a comparator circuit design which is feasible for implementation in a typical digital technology.
One conventional comparator proposed for implementation by a digital process employs wide band amplifiers where the differential signal between an input signal and a reference signal is linearly amplified to digital signal level using an open loop op-amp. The wide band amplifier may be implemented by means of a high gain stage or a cascade of low gain stages. Where a single high gain stage is used, the offset voltage and switch noise may be significant. Where a cascade of low gain stages is used, conversion time, power consumption and area are all increased. Furthermore, interfacing the stages may be problematic since the big coupling capacitors between the stages need a long time to charge up during reset, and they are difficult to implement with gate capacitance in a digital process.
In order to reduce the gain required, another conventional approach employs a latch following a set of wide band amplifiers. This approach inherits all of the advantages and disadvantages of the previously described wide band amplifier design, except that the gain required is significantly reduced.
To avoid the problem of implementing wide band amplifiers, another approach is to use only regeneration latches. For high resolution the latches must be offset cancelled. One such approach is described by Jieh-Tsorng Wu and Bruce A. Wooley in the article "A 100-MHz Pipelined CMOS Comparator", IEEE Journal of Solid-State Circuits, vol. 23, no. 6, December 1988, pp. 1,379-85. The latch described by Wu and Wooley has low resolution due to incorrect implementation of offset cancellation techniques. Therefore, such latch may be inadequate for certain applications. Furthermore, as explained in detail below, the operating point of the latch during the regeneration phase is slightly different from that during the reset phase due to clock feedthrough. Hence, even though the offset voltage has been cancelled during the reset phase, the offset voltage is no longer cancelled during the regeneration phase.
The above-described approaches for the comparator are not entirely satisfactory. It is therefore desireable to provide a comparator where the above-described difficulties are alleviated.